The reliability of single-error protected computer memories

The lifetimes of computer memories which are protected with single-error-correcting-double-error-detecting (SEC-DED) codes are studies. The authors assume that there are five possible types of memory chip failure (single-cell, row, column, row-column and whole chip), and, after making a simplifying assumption (the Poisson assumption), have substantiated that experimentally. A simple closed-form expression is derived for the system reliability function. Using this formula and chip reliability data taken from published tables, it is possible to compute the mean time to failure for realistic memory systems

Phased burst error-correcting array codes

Various aspects of single-phased burst-error-correcting array codes are explored. These codes are composed of two-dimensional arrays with row and column parities with a diagonally cyclic readout order; they are capable of correcting a single burst error along one diagonal. Optimal codeword sizes are found to have dimensions n1×n2 such that n2 is the smallest prime number larger than n1. These codes are capable of reaching the Singleton bound. A new type of error, approximate errors, is defined; in q-ary applications, these errors cause data to be slightly corrupted and therefore still close to the true data level. Phased burst array codes can be tailored to correct these codes with even higher rates than befor

On-Chip ECC for Multi-Level Random Access Memories

In this talk we investigate a number of on-chip coding techniques for the protection of Random Access Memories which use multi-level as opposed to binary storage cells. The motivation for such RAM cells is of course the storage of several bits per cell as opposed to one bit per cell [l]. Since the typical number of levels which a multi-level RAM can handle is 16 (the cell being based on a standard DRAM cell which has varying amounts of voltage stored on it) there are four bits recorded into each cell [2]. The disadvantage of multi-level RAMs is that they are much more prone to errors, and so on-chip ECC is essential for reliable operation. There are essentially three reasons for error control coding in multi-level RAMs: To correct soft errors, to correct hard errors, and to correct read errors. The source of these errors is, respectively, alpha particle radiation, hardware faults, and data level ambiguities. On-chip error correction can be used to increase the mean life before failure for all three types of errors. Coding schemes can be both bitwise and cellwise. Bitwise schemes include simple parity checks and SEC-DED codes, either by themselves or as product codes [3]. Data organization should allow for burst error correction, since alpha particles can wipe out all four bits in a single cell, and for dense memory chips, data in surrounding cells as well. This latter effect becomes more serious as feature sizes are scaled, and a single alpha particle hit affects many adjacent cells. Burst codes such as those in [4] can be used to correct for these errors. Bitwise coding schemes are more efficient in correcting read errors, since they can correct single bit errors and allow the remaining error correction power to be used elsewhere. Read errors essentially affect one bit only, since the use of Grey codes for encoding the bits into the memory cells ensures that at most one bit is flipped with each successive change in level. Cellwise schemes include Reed-Solomon codes, hexadecimal codes, and product codes. However, simple encoding and decoding algorithms are necessary, since excessive space taken by powerful but complex encoding/decoding circuits can be offset by having more parity cells and using simpler codes. These coding techniques are more useful for correcting hard and soft errors which affect the entire cell. They tend to be more complex, and they are not as efficient in correcting read errors as the bitwise codes. In the talk we will investigate the suitability and performance of various multi-level RAM coding schemes, such as row-column codes, burst codes, hexadecimal codes, Reed-Solomon codes, concatenated codes, and some new majority-logic decodable codes. In particular we investigate their tolerance to soft errors, and to feature size scaling

Remote Sensing Image Analysis via a Texture Classification Neural Network

In this work we apply a texture classification network to remote sensing image analysis. The goal is to extract the characteristics of the area depicted in the input image, thus achieving a segmented map of the region. We have recently proposed a combined neural network and rule-based framework for texture recognition. The framework uses unsupervised and supervised learning, and provides probability estimates for the output classes. We describe the texture classification network and extend it to demonstrate its application to the Landsat and Aerial image analysis domain

A digital neural network architecture using random pulse trains

A digital neural network architecture generating and processing random pulse trains, along with its unique advantages over existing comparable systems is described. In addition, test results from the VLSI implementation of its multiplication scheme are presented. These indicate that the implementation performs robustly and accurately

A digital neural network architecture using random pulse trains

A digital neural network architecture generating and processing random pulse trains, along with its unique advantages over existing comparable systems is described. In addition, test results from the VLSI implementation of its multiplication scheme are presented. These indicate that the implementation performs robustly and accurately

Analog VLSI implementation for stereo correspondence between 2-D images

Many robotics and navigation systems utilizing stereopsis to determine depth have rigid size and power constraints and require direct physical implementation of the stereo algorithm. The main challenges lie in managing the communication between image sensor and image processor arrays, and in parallelizing the computation to determine stereo correspondence between image pixels in real-time. This paper describes the first comprehensive system level demonstration of a dedicated low-power analog VLSI (very large scale integration) architecture for stereo correspondence suitable for real-time implementation. The inputs to the implemented chip are the ordered pixels from a stereo image pair, and the output is a two-dimensional disparity map. The approach combines biologically inspired silicon modeling with the necessary interfacing options for a complete practical solution that can be built with currently available technology in a compact package. Furthermore, the strategy employed considers multiple factors that may degrade performance, including the spatial correlations in images and the inherent accuracy limitations of analog hardware, and augments the design with countermeasures